c boot q 1 v dc output v dd in undervoltage gnd q 2 ? + v dd level shift out l out h v bbm boot d1 v s syn si9913 vishay siliconix document number: 71343 s-40133?rev. b, 16-feb-04 www.vishay.com 1 half-bridge mosfet driver for switching power supplies features applications 4.5- to 5.5-v operation undervoltage lockout 250-khz to 1-mhz switching frequency synchronous switch enable one input pwm signal generates both drive bootstrapped high-side drive operates from 4.5- to 30-v supply ttl/cmos compatible input levels 1-a peak drive current break-before-make circuit multiphase desktop cpu supplies single-supply synchronous buck converters mobile computing cpu core power converters standard-synchronous converters high frequency switching converters description the si9913 is a dual mosfet high-speed driver with break-before-make. it is designed to operate in high frequency dc-dc switchmode power supplies. the high-side driver is bootstrapped to handle the high voltage slew rate associated with ?floating? high-side gate drivers. each driver is capable of switching a 3000-pf load with 60-ns propogation delay and 25-ns transition time. the si9913 comes with internal break-before-make feature to prevent shoot-through current in the external mosfets. a synschronous enable pin is used to enable the low-side driver. when disabled, the out l is logic low. the si9913 is available in both standard and lead (pb)-free 8-pin soic packages for operation over the industrial operation range ( ? 40 c to 85 c). functional block diagram and truth table truth table v s syn in v outl v outh l l l l l l l h l h l h l h l l h h l h h l l l l h l h l h h h l l l h h h l h
si9913 vishay siliconix www.vishay.com 2 document number: 71343 s-40133?rev. b, 16-feb-04 absolute maximum ratings (t a = 25 c unless otherwise noted) parameter symbol limit unit low side driver supply voltage v dd 7.0 input voltage on in v in ? 0.3 to v dd +0.3 synchronous pin voltage v syn ? 0.3 to v dd +0.3 v bootstrap voltage v boot 35.0 high side driver (bootstrap) supply voltage v boot ? v s 7.0 operating junction temperature range t j ? 40 to 125 c storage temperature range t stg ? 40 to 150 c power dissipation (note a and b) p d 830 mw thermal impedance ja 125 c/w lead temperature (soldering 10 sec) 300 c notes a. device mounted with all leads soldered to p.c. board b. derate 8.3 w/ c above 25 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol limit unit bootstrap v oltage (high-side drain voltage) v boot 4.5 to 30 v logic supply v dd 4.5 to 5.5 v bootstrap capacitor c boot 100 n to 1 f ambient t emperature t a ? 40 to 85 c specifications test conditions unless specified limits parameter symbol v boot = 4.5 to 30 v, v dd = 4.5 to 5.5 v t a = ? 40 to 85 c min a typ b max a unit power supplies v dd supply v dd 4.5 5.5 i dd supply i dd1 (en) syn = h, in = h, v s = 0 v 1000 i dd supply i dd2(en) syn = h, in = l, v s = 0 v 500 a i dd supply i dd3(dis) syn = l, in = x, v s = v 500 a i dd supply i dd4(en) syn = h, in = x, v s = 25 v, v boot = 30 v 200 i dd supply i dd5(dis) syn = l, in = x, v s = 25 v, v boot = 30 v 200 i dd supply i dd(en) f in = 300 khz, syn = high, driving si4412dy 9 i dd supply i dd(dis) f in = 300 khz, syn = low, driving si4412dy 5 ma boot strap current i boot v boot = 30 v, v s = 25 v, v outh = h 0.9 3 reference voltage break-before-make reference voltage v bbm 1.1 3 v logic inputs (syn, in) input high v ih 0.7 v dd v dd + 0.3 input low v il ? 0.3 0.3 v dd v undervoltage lockout v dd undervoltage v uvl v dd rising 3.7 4.3 v v dd undervoltage hysteresis v hyst 0.4 v
si9913 vishay siliconix document number: 71343 s-40133?rev. b, 16-feb-04 www.vishay.com 3 specifications parameter unit limits test conditions unless specified v boot = 4.5 to 30 v, v dd = 4.5 to 5.5 v t a = ? 40 to 85 c symbol parameter unit max a typ b min a test conditions unless specified v boot = 4.5 to 30 v, v dd = 4.5 to 5.5 v t a = ? 40 to 85 c symbol bootstrap diode diode forward voltage vf d1 forward current = 100 ma 0.8 1 v output drive current out h source current i out( h+) v boot ? v s = 3.7 v, v outh ? v s = 2 v ? 0.4 out h sink current i out(h ? ) v boot ? v s = 3.7 v, v outh ? v s = 1 v 0.4 a out l source current i out (l+) v dd = 4.5 v, v outl = 2 v ? 0.4 a out l sink current i out(l ? ) v dd = 4.5 v, v outl = 1 v 0.6 timing (c load = 3 nf) out l off propagation delay t pdl(outl) v dd = 4 5 v 30 out l on propagation delay t pdh(outl) v dd = 4.5 v 20 out h off propagation delay t pdl(outh) v boot v s = 4 5 v 30 out h on propagation delay t pdh(outh) v boot ? v s = 4.5 v 20 ns out l turn on time t r(outl) out l = 10 to 90% 25 ns out l turn off time t f(outl) out l = 90 to 10% 25 out h turn on time t r(outh) out h ? v s = 10 to 90% 30 out h turn off time t f(outh) out h ? v s = 90 to 10% 30 notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. b. typical values are for design aid only, not guaranteed nor subject to production testing. timing waveforms out h 10% 10% 90% 90% v s out l in 50% 50% t pdh(outl) t f(outl) t pdh(outh) 90% 10% t r(outh) t pdl ( outh) t f(outh) t pdl(outl) t r(outl) 10% 90%
si9913 vishay siliconix www.vishay.com 4 document number: 71343 s-40133?rev. b, 16-feb-04 pin configuration gnd so-8 5 6 7 8 top view 2 3 4 1 out h v s in boot v dd syn out l pin description pin number name function 1 out h output drive for upper mosfet. 2 gnd ground supply 3 in cmos level input signal. controls both output drives. 4 syn synchronous enable. when logic is high, the low-side driver is enabled. 5 out l output drive for lower mosfet. 6 v dd input power supply 7 boot floating bootstrap supply for the upper mosfet 8 v s floating gnd for the upper mosfet. v s is connected to the buck switching node and the source side of the upper mosfet. ordering information part number temperature range package si9913dy bulk si9913dy-t1 ? 40 to 85 c tape and reel si9913dy-t1?e3 lead (pb)-free t ape and reel eval kit temperature range board type SI9913DB ? 40 to 85 c surface mount typical waveforms driver on switch delay si9912 tr, tf, tpd driver off switch delay v s out h out l in v s out h out l in si9912 tr, tf, tpd c l = si4412dy c l = si4412dy see figure 1 see figure 1
si9913 vishay siliconix document number: 71343 s-40133?rev. b, 16-feb-04 www.vishay.com 5 typical characteristics (25 c unless noted) 1 1 100 30 1000 10 current (ma) i dd supply current vs. frequency frequency (khz) 10 0.3 10 1 rise and fall times (ns) load capacitance (nf) rise and fall time vs. c load 3 50 40 30 20 10 0 0 1 2 3 4 5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ? 5 ? 4 ? 3 ? 2 ? 1 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output voltage drop (v) v out(h+) vs. supply supply voltage (v) supply voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 4.0 4.5 5.0 5.5 6.0 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 4.0 4.5 5.0 5.5 6.0 v out(h ? ) vs. supply v out(l+) vs. supply v out(l ? ) vs. supply supply voltage (v) supply voltage (v) output voltage drop (v) output voltage drop (v) output voltage drop (v) 0.5 a 1 a 1.5 a 0.5 a 1 a 1.5 a 2 a 0.5 a 1 a 1.5 a 2 a 0.5 a 1 a 1.5 a 2 a t r(outh) t r(outl) t f(outh) t f(outl) see figure 2 see figure 3 see figure 1 see figure 3 see figure 3 see figure 3
si9913 vishay siliconix www.vishay.com 6 document number: 71343 s-40133?rev. b, 16-feb-04 typical characteristics (25 c unless noted) 0 1 2 3 4 5 ? 50 ? 25 0 25 50 75 100 ? 5 ? 4 ? 3 ? 2 ? 1 0 ? 50 ? 25 0 25 50 75 100 output voltage drop (v) v out(h+) vs. t emperature temperature ( c) 0.0 0.5 1.0 1.5 2.0 ? 50 ? 25 0 25 50 75 100 ? 5 ? 4 ? 3 ? 2 ? 1 0 ? 50 ? 25 0 25 50 75 100 v out(h ? ) vs. t emperature v out(l+) vs. t emperature v out(l ? ) vs. t emperature output voltage drop (v) output voltage drop (v) output voltage drop (v) 0.5 a 1 a 0.5 a 1 a 1.5 a 2 a 0.5 a 1 a 1.5 a 2 a 0.5 a 1 a 1.5 a 2 a temperature ( c) temperature ( c) temperature ( c) see figure 3 see figure 3 see figure 3 see figure 3 theory of operation break-before-make function the si9913 has an internal break-before-make function to ensure that both high-side and low-side mosfets are not turned on at the same time. the high-side drive (out h ) will not turn on until the low-side gate drive voltage (measured at the out l pin) is less than v bbm , thus ensuring that the low-side mosfet is turned off. the low-side drive (out l ) will not turn on until the voltage at the mosfet half-bridge output (measured at the v s pin) is less than v bbm , thus ensuring that the high-side mosfet is turned off. under voltage lockout function the si9913 has an internal under-voltage lockout feature to prevent driving the mosfet gates when the supply voltage (at v dd ) is less than the under-voltage lockout specification (v uvl ). this prevents the output mosfets from being turned on without sufficient gate voltage to ensure they are fully on. there is hysteresis included in this feature to prevent lockout from cycling on and off.
si9913 vishay siliconix document number: 71343 s-40133?rev. b, 16-feb-04 www.vishay.com 7 bootstrap supply operation (see functional block diagram) the power to drive the high-side mosfet (q2) gate comes from the bootstrap capacitor (c boot ). this capacitor charges through d1 during the time when the low-side mosfet is on (v s is at gnd potential ), and then provides the necessary charge to turn on the high-side mosfet . c boot should be sized to be greater than ten times the high-side mosfet gate capacitance, and large enough to supply the bootstrap current (i boot ) during the high-side on time, without significant voltage droop. synchronous enable the synchronous enable pin serves to enable and disable the drive to the low-side mosfet gate. with syn high, the low-side mosfet is driven on and off in antiphase with the high-side mosfet to form a synchronous rectifier . this improves efficiency at high load currents because the flyback current is carried by the mosfet , thus eliminating the diode drop. with syn low, the low-side mosfet is held off all the time . this is particularly useful for discontinuous operation under light load or pulse skipping mode, where there is a long off time, because it prevents current flowing back from the output to ground during the off time. layout considerations there are a few critical layout considerations for these parts. firstly, the ic must be decoupled as closely as possible to the power pins. secondly the ic should be placed physically close to the high- and low-side mosfets it is driving. the major consideration is that the mosfet gates must be charged or discharged in a few nanoseconds, and the peak current to do this is of the order of 1 a. this current must flow from the decoupling and bootstrap capacitors to the ic, and from the output driver pin to the mosfet gate, returning from the mosfet source to the ic. the aim of the layout is to reduce the parasitic inductance of these current paths as much as possible. this is accomplished by making these traces as short as possible, and also running trace and its current return path adjacent to each other. applications figure 1. typical applications schematic circuit used to obtain typical rising and falling switching waveforms 8 6 7 5 1 3 2 4 out h gnd in syn v s boot v dd out l u1 si9913 +5 v c2 0.1 f pwm in gnd 1 f c5 c1 0.1 f enable 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 q1 si4412 q2 si4412 +v dc l1 15 h 0.1 f c3 15 f c4 gnd + gnd r load
si9913 vishay siliconix www.vishay.com 8 document number: 71343 s-40133?rev. b, 16-feb-04 figure 2. capacitive load test circuit used to measure rise and fall times vs. capacitance figure 3. load test schematic circuit used to measure driver output impedance 8 6 7 5 1 3 2 4 out h gnd in syn v s boot v dd out l u1 si9913 +5 v c2 0.1 f isrc isrc input gnd 8 6 7 5 1 3 2 4 out h gnd in syn v s boot v dd out l u1 si9913 +5 v c2 0.1 f pwm in gnd c load c8 c load c9
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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